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| CX20470 CDMA Baseband Analog Processor The CX20470 is a dual-mode Baseband Analog Processor (BAP) for use in Code Division Multiple Access (CDMA) and Frequency Modulated (FM) portable telephones. The device is designed to interface between the RF section and the digital processing circuitry of the telephone. The CX20470 CDMA BAP includes all of the circuitry needed to support baseband signal processing and conversions between analog and digital signals in a dual mode CDMA and FM phone. The receive section accepts analog baseband in-phase (I) and quadrature-phase (Q) signals, performs channel selection lowpass filtering, and converts the analog baseband signals into digital signals. The transmit section function provides the reverse conversions for digital input signals. In addition, the transmit section also accepts differential analog I and Q signals from baseband. The CX20470 CDMA BAP also includes digital and Phase Locked Loop (PLL) clock synthesis for 19.2 MHz, 19.68 MHz, and 19.8 MHz system clocks, general purpose Analog-to-Digital (A/D) conversions for battery and signal strength monitoring, and two PLL synthesizers The CX20470 CDMA BAP integrates an audio Coder/Decoder (CODEC) that provides signal translation between an analog voice band signal and a Pulse Code Modulation (PCM) digital signal. The CODEC is designed to perform the transmit encoding A/D conversion, together with transmit and receive filtering, for voiceband communication systems. The CODEC's audio interface consists of 3 microphone inputs, 3 audio speaker outputs, and DTMF/tone(s)/ring/side tone generation. The CODEC operation and configuration registers can be programmed by a microcontroller via an Inter-Integrated Circuit (I2C) compatible or 3-wire bus interface at any time. The CODEC also integrates the microphone amplifier and speaker post amplifier on-chip. The post amplifier is capable of driving a 32 load directly. The device is available in 100-pin BGA and 56-pin Land Grid Array (LGA) packages: * * 100-pin BGA - CDMA, FM, dual VHF synthesizers, 7-input monitor ADC, audio CODEC 56-pin LGA - CDMA, single VHF synthesizer, 2-input monitor ADC. Distinguishing Features * Dual mode for CDMA and FM operation. * Receive signal path includes: - Separate CDMA, and FM filters and ADCs - Offset control loop * Transmit signal path includes: - Configurable input interface to either digital or analog I/Q signals from the baseband modem - Selectable conversion of digital I-Q data to analog signals - Separate CDMA filters and FM filters * Two VHF PLL synthesizers: - Programmable charge pump current - Lock detector output - Operate in concert with CDMA mode operation * System clock generation and support includes: - 19.2/19/68/19.8 MHz system clock support - External CHIPx8 clocks (input to BAP) - TCXO/4 and CHIPx8 clocks powerdown capability * Audio CODEC includes: - 14-bit linear CODEC with on-chip filters meet ITU-T G.712 requirements - Switchable 3 microphone inputs with pre-amplifier gain control from -4 to 40 dB in 2 dB steps - Switchable 3 speaker outputs with programmable post-amplifiers from 0 to -30 dB in 2 dB steps, and capable of driving 32 load directly. - Programmable frequency and gain for DTMF/Tone(s)/Ring/Sidetone generation - Separate ringer output with gain control * 8-bit general purpose ADC with 7 input channels * Independent mode and operation controls for BAP and CODEC functions * Low power consumption in all operation modes * Baseband modem interface compatibility includes: - MSM2300/MSM3000 - MSM3100 * Single supply voltage from 2.7 V to 3.6 V * Operating temperature of -40 C to +85 * Package options include: - 100-pin BGA - 56-pin LGA The device package pinout for each of these are shown in Figures 1 and 2. A general block diagram of the CX20470 BAP is shown in Figure 3. Applications * Cellular and Advanced Mobile Phone System (AMPS) band phones * Dual band PCS/cellular CDMA * Dual mode/dual band Data Sheet Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change Order No. 101106A August 24, 2000 CX20470 CDMA BAP 1 2 3 4 5 6 7 8 9 10 A IOFFSET VREFP AVDD_RX ADC_IN2 ADCSEL0 RXQD0 SCLK RXID1 RXID0 CHIPX8 B QOFFSET VREFN RBIAS ADC_IN3 ADCSEL1 RXQD1 RXID2 RXID3 TXCLK/ DVDD C RXQ/ RXI/ AVSS_RX VC RXQD2 SEL_SI SINO/SDA DVSS ADCCLK ADCDATA D ADC_IN0 RXQ RXI ADC_IN4 POR CS/AD RXFMSTB ADCENA FMCLK ADCSEL2 E AVDDSY2 RXPDOUT RXPLLIN/ ADC_IN1 RXQD3 TXD7 PCMIN TXD6 RXQFMDA RXIFMDA F AVDDSY1 TXPDOUT AVSSSY2 RXPLLIN AVSSSY1 AVSS_TX PDBTCXO PCMOUT TXD5 MCLK G AVDDMC TXPLLIN AVSSMC TXPLLIN/ MC_BG MICINN FM_MOD TXD4 TXD2 SYNC H LINEOP LINEON SPKRON TEST/ MICINP PLLFILTR TXI ADC_IN6 TXD3 TXD1 J SPKROP SYNENA SLEEP/ IDLE/ LINEINN AVDD_TX TXQ SYNPRES FM/ TXD0 K LOCK SYNDATA SYNCLK MC_BIAS LINEINP TXQ/ TXI/ ADC_IN5 TCXO TCXO/4 C825 Figure 1. CX20470 BAP Pinout - 100-Pin BGA Package 2 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 101106A August 24, 2000 CDMA BAP CX20470 ADCSEL0 IOFFSET RXQD3 RXQD2 RXQD1 RXQD0 VREFN VREFP RBIAS RXID3 RXID2 RXID1 44 56 55 54 53 52 51 50 49 48 47 46 45 QOFFSET RXQ/ RXQ RXI/ RXI ADC_IN1 ADC_IN0 AVSSSY1 TXPDOUT AVDDSY1 TXPLLIN/ TXPLLIN SYNENA LOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 43 RXID0 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VC CHIPx8 TXCLK/ DVDD DVSS ADCDATA ADCCLK ADCENA TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 15 16 17 18 19 20 21 22 23 24 25 26 27 TXQ/ TXQ TXI/ TXI TCXO SYNCLK SYNDATA AVSS_TX AVDD_TX PDBTCXO TCXO/4 SLEEP/ TXD0 IDLE/ 28 C847 Figure 2. CX20470 BAP Pinout - 56-Pin LGA Package RF Chipset CX20470 PA RF251/ RF261 BAP RF250/ RF260 Codec Speaker Microphone Baseband ASIC CNXT043 Figure 3. CX20470 General Block Diagram 101106A August 24, 2000 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 3 CX20470 CDMA BAP Technical Description The CX20470 consists of a CDMA transmit and receive path, FM transmit and receive path, Intermediate Frequency (IF) PLL synthesizer section, an auxiliary control section, and an audio CODEC section. Each of these functional sections is detailed in the complete CX20470 system block diagram shown in Figure 4. CDMA Transmit Path The CDMA transfer signal path accepts two different interface formats from the baseband ASIC: analog signal and digital data. The interface format configuration can be controlled through BAP control register. For analog signal interface, the BAP accepts I and Q analog transmit signals from the digital modem and performs transmit lowpass filters with a bandwidth of 1 MHz for image rejection. The I and Q filtered signals are then output to the transmitter. For digital signal interface, the BAP transmit signal path accepts digital I and Q data baseband signals form the baseband modem and outputs analog I and Q components to the IF transmitter. Eight bits of I and Q transmit data are input to the CDMA Digital-toAnalog Converters (DACs) by multiplexing over and 8-bit input port on the BAP. At the falling edge of the transmit clock input (TxCLK/), the 8-bit parallel transmit data is registered into I DAC, and, at the rising edge, registered into Q DAC. The outputs from I DAC and Q DAC are followed by transmit low-pass reconstruction filters with a bandwidth of 630 kHz for removal of unwanted frequency components. The precise I and Q signals are output to the transmitter. CDMA Receive Path The BAP receive path is designed to accept I and Q baseband analog components. These signals are input into lowpass filters specifically designed for CDMA. These filters, when combined with the external IF bandpass filtering, provide the necessary receiver passband, rejection band amplitude, and phase response. The control of DC offset is made to the I and Q signals from the inputs IOFFSET and QOFFSET. Analog voltages at these inputs adjust the offset before the A/D conversion. Two identical 4-bit flash ADCs sample the I and Q signals at a rate of 9.8304 MHz (CHIPx8) and output the four bits each in parallel to a baseband device. FM Transmit Path The FM transmit signal path accepts two different interface formats from the baseband ASIC: analog signal and digital data. The interface format configuration can be controlled through BAP control register. For the analog signal interface, the BAP accepts I and Q analog signals from the digital modem and perform transmit low-pass 4 filters. The I and Q transmit filters are then output to the transmitter. For the digital signal interface, the FM modulation signal is created from an 8-bit DAC, which is the Q signal DAC re-used from the CDMA section. The DAC rate is determined from the transmit clock input (TXCLK/) and the digital input is 8-bit parallel. The DAC analog output is the analog output FM modulation signal used to directly control a transmit VCO using external components. FM Receive Path The receive path for FM operation is similar to that for CDMA operation. The differences are that the receive path uses 15 kHz bandwidth low-pass filters and provides 8-bit serial output ADCs. These ADCs sample the analog I and Q signals at a rate determined by the strobe (RXFMSTB). The digital data is output serially and determined by the FMCLK beginning with the Most Significant Bit (MSB) of the result. IF PLL Synthesizer Section Two identical and independent PLL synthesizers are provided to synthesize the transmit and receive IF frequencies. Each contains a dual modulus divide by 16/17 prescaler, a 13-bit R counter, a 17bit N counter, a phase detector, and a charge pump current and lock detector configuration. The synthesizers accept differential VCO inputs up to 640 MHz and a shared TCXO reference input. CDMA Auxiliary Section The auxiliary section of the CDMA BAP includes mode control logic, a general purpose ADC, and clock generation. Mode Control Logic. The BAP has several operating modes, each one selected by one of three digital inputs: FM, IDLE, and SLEEP. * * * * * CDMA RxTx or FM RxTx mode: When a call is in progress. IDLE mode: When a call is not in progress but the telephone is ready to answer a call. SLEEP mode (low-power mode): Calls cannot be received but the digital processor and keypad are enabled. CDMA slotted paging mode: IDLE mode only for paging slot, other time SLEEP mode. Power-down mode: Device is in standby mode (leakage current consumption only). General Purpose ADC. The BAP provides an 8-bit resolution ADC that can be applied to monitor battery level, temperature, and/or sensors. Clock Generation. The CDMA BAP provides a digital and/or PLL clock synthesis network to generate TCXO/4 and CHIPx8 signals from a 19.2 MHz, 19.68 MHz, or 19.8 MHz system clock. The clock generation configuration can be programmed via the synthesizer's three-wire serial interface. 101106A August 24, 2000 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change CDMA BAP CX20470 Audio CODEC Section The CODEC serves as an interface between a voice device and a digital processor system. The CODEC provides a bi-directional interface between voice/audio and a digital system processor. It receives audio signals from sources such as microphones, digitizes the signals, and outputs them to a host processing system. The CODEC receives digital signals from the digital processing system (MSM ASIC or equivalent), converts the signal to analog, and outputs the signal to a device such as an earpiece or a speaker. As shown in Figure 5, CODEC operations can be divided into four groups: transmit (ADC) channel, receive (DAC) channel, timing and control, and power control. CODEC Transmit Section. The transmit section is designed to interface directly with a microphone and/or an external audio source at the same time. The microphone input or external source signal can be selected as the audio input signal. The input signal is buffered and amplified with a provision to set the amplifier gain to accommodate a range of signal input levels. The amplified signal is then anti-aliased and bandpass filtered and applied to the input of a 14-bit linear A/D converter. The digital converted data is then clocked out as a serial data stream (PCMOUT) to the digital system processor. CODEC Receive Section. The receive section collects a frame of serial data on the PCMIN and converts it to the analog signal through a linear D/A converter. The analog converted signal is then lowpass filtered to provide out-of-band rejection and smoothing. The filtered signal is sent to the speaker or the line driver amplifier. Both amplifiers have a differential output with adjustable gain control. CODEC Configuration and Control Interface Section. CODEC operation mode and configuration control registers can be easily programmed directly from a digital system processor through an I2C -bus compatible or three-wire serial bus interface. The serial interface types are pin-selectable between 3-wire bus or I2C-bus interface. Electrical and Mechanical Specifications Signal pin assignments and functional pin descriptions are described in Table 1 (100-pin BGA) and Table 2 (56-pin LGA). The absolute maximum ratings of the CX20470 are provided in Table 3. The recommended operating conditions are specified in Table 4. Electrical specifications are provided in Table 5. Tables 6 through 9 specify input and output signal levels and electrical characteristics. A system block diagram is provided in Figure 4 and an audio CODEC block diagram is presented in Figure 5. Package dimensions for the CX20470 are shown in Figure 6 (100-pin BGA) and Figure 7 (56-pin LGA). Electrostatic Discharge (ESD) Sensitivity The CX20470 is a Class 1 device. The following ESD precautions are required: * * * * Protective outer garments. Handle device in ESD safeguarded work area. Transport device in ESD shielded containers. Monitor and test all ESD protection equipment. Treat the CX20470 BAP as extremely sensitive to ESD since ESD sensitivity has not yet been determined for this device. 101106A August 24, 2000 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 5 CX20470 CDMA BAP FM_Mod Low Pass FIlter Mux ( TXIIN ) ( TXIIN/ ) 8 ( TXD[7:0] ) TXCLK/ (4.9 MHz/120 KHz) CDMA/FM Mode TX_Q TX_Q/ 2 Low Pass Filter Transmit Filter 8 Bit DAC TX_I TX_I/ 2 Low Pass Filter Transmit Filter 8 Bit DAC 8 ADC 40 KHz P/S Mux ( TXQIN ) ( TXQIN/ ) Anti-Alias Filter FM Filter 360 KHz 360 KHz RXIFMDATA FMCLK RXQFMDATA RXFMSTB RXID[3:0] Anti-Alias Filter FM Filter ADC 8 P/S 40 KHz 360 KHz 40 KHz RX_I RX_I/ 2 Anti-Alias Filter CDMA Filter ADC 4 RX_Q RX_Q/ 2 Anti-Alias Filter CDMA Filter ADC 4 RXQD[3:0] 2 DC cancellation 19.2 MHz 19.68 MHz 19.8 MHz PLL 2:1 Digital Synthesis CHIPX8 Int I Offset Q Offset ( CHIPX8_EXT ) CHipx8 Select Digital Synthesis CHIPX8 TCXO/4 TCXO RXPD_OUT RXPLL_IN 2 / N3 Phase Detector / R3 IREF ( IREF ) TXPD_OUT 2 TXPLL_IN ( RINGER ) ( SPKR2O ) SPKR1O LINEO ( MIC1IN ) MIC2IN LINEIN SDA SCL SEL_SI CS_AD ( ADCIN[6:0] ) 7 3 ADCSEL[2:0] Analog Mux 8 Bit ADC 2 2 Mode Control 2 2 CODEC / N2 Phase Detector / R2 & LOCK SYN_ENABLE PLL & Analog Mux Control 2 SYN_DATA SYN_CLK SYN_PRESET MCLK/SYNC SIN SOUT SLEEP/ IDLE/ FM/ PDBTCXO ( TEST/ ) ADCCLK ADCDATA ADCENA Key: Signals in the ( ) represent multiplexed I/O pins Figure 4. CX20470 System Block Diagram (100-Pin BGA Package) 6 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 101106A August 24, 2000 CDMA BAP CX20470 Transmit and Receive Channel Mic Microphone PreAmplifier Transmit Filters Transmit Encoding PCM Output Logic Voice Analog Interface Speaker Speakers Amplifier Receive Filters Sidetone Gain PCM Interface Digital System Processor PCM Input Logic Receive Encoding DTMF/Tone/Ring Ringer Ring Tone/Ring/DTMF Generator Timing and Control Control Interface CODEC Figure 5. CX20470 BAP Audio CODEC Block Diagram (100-Pin BGA Package) Table 1. CX20470 BAP Signal Description: 100-Pin BGA Package (1 of 4) Pin # D3 C2 D2 C1 B8 B7 A8 A9 E5 C5 B6 A6 D7 D9 E10 E9 RXI RXI/ RXQ RXQ/ RXID3 RXID2 RXID1 RXID0 RXQD3 RXQD2 RXQD1 RXQD0 RXFMSTB FMCLK RXIFMDA RXQFMDA Name A,I,Z A,I,Z A,I,Z A,I,Z I/O Type Receive Signal Path Description Baseband receive in-phase analog differential input (+). Baseband receive in-phase analog differential input (-). Baseband receive quadrature analog differential input (+). Baseband receive quadrature analog differential input (-). Receive CDMA in-phase 4-bit A/D output (bit 3) Receive CDMA in-phase 4-bit A/D output (bit 2) Receive CDMA in-phase 4-bit A/D output (bit 1) Receive CDMA in-phase 4-bit A/D output (bit 0) Receive CDMA quadrature 4-bit A/D output (bit 3) Receive CDMA quadrature 4-bit A/D output (bit 2) Receive CDMA quadrature 4-bit A/D output (bit 1) Receive CDMA quadrature 4-bit A/D output (bit 0) Receive FM data strobe input. Receive FM data clock input. Receive FM I serial data output. Receive FM Q serial data output. Transmit Signal Path Configurable pin. Can be configured to be transmit digital 8-bit data from MSM (bit 7) for digital transmit data input mode, or IREF current output for MSM3100 interface mode Configurable pin. Can be configured to be transmit digital 8-bit data from MSM (bit 6) for digital TX data input, or TX I channel analog differential input (+) for MSM3100 interface mode. D,O,L D,O,L D,O,L D,O,L D,O,L D,O,L D,O,L D,O,L D,I,Z D,I,Z D,O,L D,O,L E6 E8 TXD7 or IREF TXD6 or TXIIN D,I or A,O D,I or A,I 101106A August 24, 2000 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 7 CX20470 CDMA BAP Table 1. CX20470 BAP Signal Description: 100-Pin BGA Package (2 of 4) Pin # Name I/O Type Receive Signal Path (continued) F9 TXD5 or TXIIN/ D,I or A,I Configurable pin. Can be configured to be transmit digital 8-bit data from MSM (bit 5) for digital TX data input, or TX I channel analog differential input (-) for MSM3100 interface mode. Configurable pin. Can be configured to be transmit digital 8-bit data from MSM (bit 4) for digital TX data input or TX Q channel analog differential input (+) for MSM3100 interface mode. Configurable pin. Can be configured to be transmit digital 8-bit data from MSM (bit 3) for digital TX data input or TX Q channel analog differential input (-) for MSM3100 interface mode. Transmit digital 8-bit data from MSM (bit 2) Transmit digital 8-bit data from MSM (bit 1) Transmit digital 8-bit data from MSM (bit 0) Configurable pin. Can be configured to be negative differential transmit clock input or CHIPx8 clock input. Baseband transmit in-phase analog differential output. Baseband transmit in-phase analog differential output. Baseband transmit quadrature analog differential output (+). Baseband transmit quadrature analog differential output (-). FM modulation analog output signal. Dual VHF and Clock Synthesizers F4 E3 E2 H6 F2 G2 G4 J8 J2 K2 K3 K1 J9 J3 J4 F7 H4 RXPLLIN RXPLLIN/ RXPDOUT PLLFILTR TXPDOUT TXPLLIN TXPLLIN/ SYNPRES SYNENA SYNDATA SYNCLK LOCK FM/ SLEEP/ IDLE/ PDBTCXO TEST/ or SPKR2O A,I,Z A,I,Z A,O,Z A,O,Z A,O A,I,Z A,I,Z D,I,Z D,I,Z D,I,Z D,I,Z A,O,L D,I,Z D,I,Z D,I,Z D,I,Z D,I or A,O Receive synthesizer divider differential input (+). Receive synthesizer divider differential input (-). Receiver synthesizer (RX PLL) phase detector charge pump output. Loop filter for clock PLL when enabled. Transmit synthesizer (TX PLL) phase detector charge pump output. Transmit synthesizer divider differential input (+) from the external VCO buffer. Transmit synthesizer divider differential input (-) from the external VCO buffer. When high, disables the synthesizers. Synthesizer three-wire serial interface enable. Synthesizer three-wire serial interface data input. Synthesizer three-wire serial interface clock input. Lock detect indicator for the receive and transmit VHF synthesizers. Mode Control FM or CDMA mode select input. CDMA sleep mode is enabled when this input pin is low and FM/ is high. CDMA idle or FM idle modes are enabled when this input is low and SLEEP/ is high. When this signal is activated, the BAP will power-down its TCXO buffer input clock. Configurable pin. Can be configured to be test purposes control pin or single-ended speaker output System Clock and Synthesized Clock K9 A10 K10 TCXO CHIPx8 TCXO/4 A,I,Z D,O,L D,O,L TCXO 19.2/19.68/19.8 MHz clock input. 9.8304 MHz digital clock output. This signal, typically 4.92 MHz, is digitally synthesized from the TCXO input clock. Description G8 TXD4 or TXQIN D,I or A,I H9 G9 H10 J10 B9 H7 K7 J7 K6 G7 TXD3 or TXQIN/ TXD2 TXD1 TXD0 TXCLK/ or CHIPx8IN TXI TXI/ TxQ TxQ/ FM_MOD D,I or A,I D,I,Z D,I,Z D,I,Z D,I,Z A,O,Z A,O,Z A,O,Z A,O,Z A,O,S 8 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 101106A August 24, 2000 CDMA BAP CX20470 Table 1. CX20470 BAP Signal Description: 100-Pin BGA Package (3 of 4) Pin # D8 C10 C9 D10 B5 A5 H8 K8 D4 B4 A4 E4 D1 A1 B1 A2 B3 B2 F10 G10 F8 E7 A7 C7 C6 D6 D5 G6 H5 J5 K5 G5 K4 H3 J1 H2 H1 ADCENA ADCDATA ADCCLK ADCSEL2 ADCSEL1 ADCSEL0 ADC_IN6 or RINGER ADC_IN5 or MIC2IN ADC_IN4 ADC_IN3 ADC_IN2 ADC_IN1 ADC_IN0 IOFFSET QOFFSET VREFP RBIAS VREFN MCLK SYNC PCMOUT PCMIN SCLK SINO/SDA SEL_SI CS/AD POR MICINN MICINP LINEINN LINEINP MC_BG MC_BIAS SPKRON SPKROP LINEON LINEOP Name D,I,Z I/O Type General Purpose ADC Monitor A/D enable input. Monitor A/D data output to MSM. Monitor A/D clock output to MSM. D,O,Z D,O,Z D,I,Z D,I,Z D,I,Z A,I or D,O,Z A,I,Z A,I,Z A,I,Z A,I,Z A,I,Z A,I,Z A,I,Z A,I,Z Decoupling Decoupling Decoupling D,I,Z D,I,L D,O,L D,I,Z D,I,Z D,B,L D,I,Z D,I,Z D,I,Z A,I,Z A,I,Z A,I,Z A,I,Z Decoupling A,O,Z A,O,Z A,O,Z A,O,Z A,O,Z Description Monitor A/D digital 3-bit input that controls the input MUX selection (bit 2). Monitor A/D digital 3-bit input that controls the input MUX selection (bit 1). Monitor A/D digital 3-bit input that controls the input MUX selection (bit 0). Configurable pin. Can be configured to be monitor A/D analog independent input for voltage sense input or RINGER output signal Configurable pin. Can be configured to be monitor A/D analog independent input for voltage sense input or second single-ended microphone input. Monitor A/D analog independent input for voltage sense input Monitor A/D analog independent input for voltage sense input Monitor A/D analog independent input for voltage sense input Monitor A/D analog independent input for voltage sense input Monitor A/D analog independent input for voltage sense input Offset and Bias I ADC input offset adjust signal input. Q ADC input offset adjust signal input. Positive reference bypass line. Analog input sets the system bias current via an external resistor. Negative reference bypass line. Audio CODEC CODEC master clock input, typically 2.048 MHz. Frame synchronization clock input, typically 8 kHz. Serial PCM data output. Serial PCM data input. I2C bus or three-wire serial clock used to synchronize data transfer from and to CODEC. Three-wire or I2C input data path. User generated signal pin to select either I2C bus or three-wire interface configuration. When in I2C bus configuration, this signal is used as bit 0 of the CODEC's device address. CODEC power-down signal. First negative high-impedance input to transmit pre-amplifier for microphone connection. First positive high-impedance input to transmit pre-amplifier for microphone connection Third negative high-impedance input to transmit pre-amplifier for audio line input connection. Third positive high-impedance input to transmit pre-amplifier for audio line input connection. MIC band gap. Microphone bias voltage. Earpiece differential (-) output. Earpiece differential (+) output. Secondary differential (-) output. Secondary differential (+) output. 101106A August 24, 2000 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 9 CX20470 CDMA BAP Table 1. CX20470 BAP Signal Description: 100-Pin BGA Package (4 of 4) Pin # G1 G3 F5 F3 F1 E1 F6 J6 C8 B10 A3 C3 C4 AVDDMC AVSSMC AVSSSY1 AVSSSY2 AVDDSY1 AVDDSY2 AVSS_TX AVDD_TX DVSS DVDD AVDD_RX AVSS_RX VC Name PG PG PG PG PG PG PG PG PG PG PG PG I/O Type Power and Ground Power supply voltage. Ground. Analog ground VSS input. Analog ground VSS input. Analog VDD input. Analog VDD input. Analog ground input. Analog VDD input. Digital ground VSS input. Digital VDD input. Analog VDD input. Analog ground VSS input. Analog ground bypass line. Description Decoupling I/O Type Descriptions: A: Analog O: Output B: Bi-directional PG: Power and ground D: Digital Z: High impedance H: Logic high level R: Forced to VREF I: Input S: Forced to AVSS L: Logic low level 10 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 101106A August 24, 2000 CDMA BAP CX20470 Table 2. CX20470 BAP Signal Description: 56-Pin LGA Package (1 of 2) Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 QOFFSET RXQ/ RXQ RXI/ RXI ADC_IN1 ADC_IN0 AVSSSY1 TXPDOUT AVDDSY1 TXPLLIN/ TXPLLIN SYNENA LOCK SYNDATA SYNCLK IDLE/ SLEEP/ AVSS_TX AVDD_TX PDBTCXO TXQ/ TXQ TXI/ TXI TCXO TCXO/4 TXD0 TXD1 TXD2 TXD3 or TXQIN/ Name A,I,Z A,I,Z A,I,Z A,I,Z A,I,Z A,I,Z A,I,Z PG A,O P,G A,I,Z A,I,Z D,I,Z I/O Type Description Q ADC input offset adjust signal input. Baseband receive quadrature analog differential input. Baseband receive quadrature analog differential input. Baseband receive analog differential input. Baseband receive analog differential input. Monitor A/D analog independent input for voltage sense input. Monitor A/D analog independent input for voltage sense input. Analog ground VSS input. Transmit synthesizer (TX PLL) phase detector charge pump output. Analog VDD input. Transmit synthesizer divider differential input (-) from the external VCO buffer. Transmit synthesizer divider differential input (+) from the external VCO buffer. Synthesizer three-wire serial interface enable. Lock detect indicator for the receive and transmit VHF synthesizers. Synthesizer three-wire serial interface data input. Synthesizer three-wire serial interface clock input. CDMA idle or FM idle modes are enabled when this input is low and SLEEP/ is high. CDMA sleep mode is enabled when this input pin is low and FM/ is high. Analog ground input. Analog VDD input. When this signal is activated, the BAP will power-down its TCXO buffer input clock. Baseband transmit quadrature analog differential output (-). Baseband transmit quadrature analog differential output (+). Baseband transmit in-phase analog differential output. Baseband transmit in-phase analog differential output. TCXO 19.2/19.68/19.8 MHz clock input. This signal, typically 4.92 MHz, is digitally synthesized from the TCXO input clock. Transmit digital 8-bit data from MSM (bit 0). Transmit digital 8-bit data from MSM (bit 1). Transmit digital 8-bit data from MSM (bit 2). Configurable pin. Can be configured to be transmit digital 8-bit data from MSM (bit 3) for digital TX data input or TX Q channel analog differential input (-) for MSM3100 interface mode. Configurable pin. Can be configured to be transmit digital 8-bit data from MSM (bit 4) for digital TX data input or TX Q channel analog differential input (+) for MSM3100 interface mode. Configurable pin. Can be configured to be transmit digital 8-bit data from MSM (bit 5) for digital TX data input, or TX I channel analog differential input (-) for MSM3100 interface mode. Configurable pin. Can be configured to be transmit digital 8-bit data from MSM (bit 6) for digital TX data input, or TX I channel analog differential input (+) for MSM3100 interface mode. Configurable pin. Can be configured to be transmit digital 8-bit data from MSM (bit 7) for digital transmit data input mode, or IREF current output for MSM3100 interface mode A,O,L D,I,Z D,I,Z D,I,Z D,I,Z PG PG D,I,Z A,O,Z A,O,Z A,O,Z A,O,Z A,I,Z D,O,L D,I,Z D,I,Z D,I,Z D,I or AI 32 TXD4 or TXQIN D,I or A,I 33 TXD5 or TXIIN/ D,I or A,I 34 35 TXD6 or TXIIN TXD7 or IREF D,I or A,I D,O or A,O 101106A August 24, 2000 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 11 CX20470 CDMA BAP Table 2. CX20470 BAP Signal Description: 56-Pin LGA Package (2 of 2) Pin # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 ADCENA ADCCLK ADCDATA DVSS DVDD TXCLK/ or CHIPx8IN CHIPx8 RXID0 RXID1 RXID2 RXID3 RXQD0 RXQD1 RXQD2 RXQD3 ADCSEL0 VC RBIAS VREFP VREFN IOFFSET Name A,I,Z I/O Type Monitor A/D enable input. Monitor A/D clock output to MSM. Monitor A/D data output to MSM. Digital ground VSS input. Digital VDD input. A,O,Z A,O,Z PG PG D,I,Z D,O,L D,O,L D,O,L D,O,L D,O,L D,O,L D,O,L D,O,L D,O,L D,I,Z Decoupling Decoupling Decoupling Decoupling A,I,Z Description Configurable pin. Can be configured to be negative differential transmit clock input or CHIPx8 clock input. 9.8304 MHz digital clock output. Receive CDMA in-phase 4-bit A/D output (bit 0). Receive CDMA in-phase 4-bit A/D output (bit 1). Receive CDMA in-phase 4-bit A/D output (bit 2). Receive CDMA in-phase 4-bit A/D output (bit 3). Receive CDMA quadrature 4-bit A/D output (bit 0). Receive CDMA quadrature 4-bit A/D output (bit 1). Receive CDMA quadrature 4-bit A/D output (bit 2). Receive CDMA quadrature 4-bit A/D output (bit 3). Monitor A/D digital 3-bit input that controls the input MUX selection (bit 1). Analog ground bypass line. Analog input sets the system bias current via an external resistor. Positive reference bypass line. Negative reference bypass line. I ADC input offset adjust signal input. I/O Type Descriptions: A: Analog O: Output B: Bi-directional PG: Power and ground D: Digital Z: High impedance H: Logic high level R: Forced to VREF I: Input S: Forced to AVSS L: Logic low level 12 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 101106A August 24, 2000 CDMA BAP CX20470 Table 3. Absolute Maximum Ratings Parameter Power supply Analog input voltage Digital input voltage Input current per pin Output current per pin Short circuit duration, to GND or VDD Ambient temperature (power applied) Storage temperature -55 -65 Minimum -0.3 -0.3 -0.3 -10 -50 Maximum 3.6 VDD+0.3 VDD+0.3 +10 +50 1 +125 +150 Units V V V mA mA sec C C Table 4. Recommended Operating Conditions Parameter Power supply for full performance Operating junction temperature Operating ambient temperature Min 2.7 -40 -40 Typical 3.0 Max 3.6 +100 +85 Units V C C Table 5. CX20470 BAP Electrical Specifications (1 of 2) Parameter Supply current - CDMA RxTx Supply current - CDMA idle Supply current - CDMA sleep Supply current - FM RxTx Supply current -FM idle Supply current - power down Supply current - RxTx Supply current - CODEC standby Supply current - CODEC power down Symbol IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 Test Condition Min Typical 12 (Note 1) 8 (Note 1) 0.5 7 (Note 1) 4 (Note 1) 15 0.7 <1 <1 Max Units mA mA mA mA mA A mA A A Power Supply Current (BAP only, Without CODEC) Power Supply Current (CODEC only, Without BAP) IDD7 IDD10 IDD11 101106A August 24, 2000 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 13 CX20470 CDMA BAP Table 5. CX20470 BAP Electrical Specifications (2 of 2) Parameter Logic high input voltage Logic low input voltage Logic high output voltage Logic low output voltage Logic input leakage current Digital input capacitance Digital output load capacitance Digital output load resistance Offset adjust input impedance (IOFFSET, QOFFSET) TCXO input capacitance TCXO input resistance TCXO input signal level RxI, RxQ single-ended input resistance RxI, RxQ single-ended input capacitance RxI, RxQ single-ended input resistance RxI, RxQ single-ended input capacitance TxI, TxQ single-ended output resistance TxI, TxQ single-ended output capacitance FM_MOD output resistance FM_MOD output capacitance 0.7 CDMA mode CDMA mode FM mode FM mode 0.7 140 5 0.5 28 40 5 200 5 1 5 1 5 1.3 1.3 260 52 Symbol AC/DC VIH VIL VOH VOL IIL CID CLD RLD ZIOA Test Condition Min 0.7X Typical Max Units V 0.3X 2.7 0.4 VDD = Maximum, VIN = GND to VDD -100 +100 10 15 100 100 10 V V V A pF pF k k pF k Vp-p k pF k pF k pF k pF Note 1: Supply current also includes two VHF synthesizers operating in the highest frequency mode. For lower frequency modes, the current consumption of each VHF synthesizer is reduced by 0.5 mA. Table 6. Absolute Input Signal Levels at MICIN/LINEIN Amplifier Output 0 dBm0 level Overload level 0 dBm0 level Overload level Condition Transmit amplifier is programmed for 0 dB gain Transmit amplifier is programmed for 40 dB gain Min Typical 492.6 707.1 3.694 5.302 Max Units mVrms mVrms Table 7. CODEC Analog Input Interface Electrical Characteristics Description Input offset voltage at MIC1IN, MIC2IN, and LINEIN audio inputs Input bias current at MIC1IN, MIC2IN, and LINEIN audio inputs Input capacitance at MIC1IN, MIC2IN, and LINEIN audio inputs Output source current Microphone bias supply voltage Input impedance (fully differential) Microphone mute attenuation Isolation between MICIN and LINEIN inputs 50 -80 74 1 2.0 Min -5 -200 Typical Max +5 +200 Units mV nA pF mA V k dB dB 1.5 14 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 101106A August 24, 2000 CDMA BAP CX20470 Table 8. Absolute Output Signal Levels at SPKRO/LINEO Amplifier Input 0 dBm0 level 0 dBm0 level Condition Receive amplifier is programmed for 0 dB gain Transmit amplifier is programmed for -30 dB gain Min Typical 1.06 61.85 Max Units mVrms mVrms Table 9. CODEC Analog Output Interface Electrical Characteristics Description AC voltage output (peak-to-peak) Output offset voltage (single ended) relative to ground at SPKR10, SPKR20, and LINEO Output offset voltage (fully differential) relative to ground at speaker output (SPKRO) and line output (LINEO) Maximum output current for SPKR1O output (rms) Maximum output current for SPKR2O output (rms) Maximum output current for LINEO output (rms) Output resistance at SPKR1O, LINEO Output resistance at SPKR2O Output load resistance Output load capacitance Gain change (when power-down mode, max level when muted) Speaker mute attenuation -60 -80 30 50 1 0.5 -30 -50 Min Typical Max 4 +30 +50 10 10 46 Units Vp-p mV mV mA mA mA pF dB dB 7.20 A1 Ball Pad Corner 10.00 1.40 0.10 0.70 0.05 0.40 0.80 |DATUM B| A B C D E 7.20 F 0.40 10.00 DATUM A G H J 0.80 K 10 DETAIL A 9 8 7 6 5 4 3 2 1 TOP VIEW SIDE VIEW BOTTOM VIEW 0.10 0.10 SEATING PLANE 0.36 0.05 100X 0.46 0.05 All measurements are in millimeters DETAIL A C606 Figure 6. CX20470 BAP Package Dimensions - 100-Pin BGA 101106A August 24, 2000 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 15 CX20470 CDMA BAP Figure 7. CX20470 BAP Package Dimensions - 56-Pin LGA 16 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 101106A August 24, 2000 CDMA BAP CX20470 Ordering Information Model Name CX20470 100-pin BGA CX20470 56-pin LGA Manufacturing Part Number Product Revision (c) 2000, 2001, 2002, Skyworks Solutions, Inc. All Rights Reserved. Information in this document is provided in connection with Skyworks Solutions, Inc. ("Skyworks") products. These materials are provided by Skyworks as a service to its customers and may be used for informational purposes only. Skyworks assumes no responsibility for errors or omissions in these materials. Skyworks may make changes to its products, specifications and product descriptions at any time, without notice. Skyworks makes no commitment to update the information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from future changes to its products and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as may be provided in Skyworks' Terms and Conditions of Sale for such products, Skyworks assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF SKYWORKSTM PRODUCTS INCLUDING WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. SKYWORKS FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THESE MATERIALS. SkyworksTM products are not intended for use in medical, lifesaving or life-sustaining applications. Skyworks' customers using or selling SkyworksTM products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale. The following are trademarks of Skyworks Solutions, Inc.: SkyworksTM, the Skyworks symbol, and "Breakthrough Simplicity"TM. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. Additional information, posted at www.skyworksinc.com, is incorporated by reference. 101106A August 24, 2000 Skyworks - Preliminary Proprietary Information and Specifications are Subject to Change 17 General Information: Skyworks Solutions, Inc. 4311 Jamboree Rd. Newport Beach, CA 92660-3007 www.skyworksinc.com |
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